1. Field of the Invention
The invention relates generally to complementary metal oxide semiconductor (CMOS) structures. More particularly, the invention relates to CMOS structures with enhanced performance.
2. Description of the Related Art
Complementary metal oxide semiconductor structures typically include a mated pair comprising one each of a p-channel and an n-channel field effect transistor. Due to the complementary doping of such a field effect transistor pair, CMOS devices generally provide low energy consumption semiconductor circuits. In turn, low energy consumption semiconductor circuits are particularly desirable within the context of microprocessors, other logic applications and portable electronics applications.
Similarly with other semiconductor devices, a trend also exists within CMOS device fabrication to enhance field effect transistor performance. In that regard, one variable of field effect transistor fabrication that is known to influence field effect transistor performance is a crystallographic orientation of a semiconductor substrate upon which a field effect transistor is fabricated. The different charge carrier modes within field effect transistors provide that p-FETs and n-FETs are advantageously fabricated upon different semiconductor substrate channel crystallographic orientations in order to provide individually optimized performance of p-FETs and n-FETs. For enhanced CMOS performance, it is thus desirable to provide a semiconductor substrate that accommodates multiple crystallographic orientations.
Examples of semiconductor structures that include multiple transistors having different performance characteristics incident to use of differing crystallographic orientation channel regions are known in the art. For example, Doris et al., in U.S. Pat. No. 6,911,383 teaches a semiconductor structure that comprises both a planar field effect transistor and a finFET located upon a semiconductor-on-insulator semiconductor substrate. The planar FET and the finFET may be fabricated using different crystallographic orientations for the planar field effect transistor channel and a semiconductor fin that comprises the finFET channel.
Due to ease of fabrication and low energy consumption, CMOS devices are likely to continue to be prevalent within the semiconductor fabrication art. Similarly, due to significant performance advantages, the fabrication of complementary p-FET and n-FET CMOS transistors with different semiconductor substrate channel crystallographic orientations is also a desirable goal within the semiconductor fabrication art. In light of the foregoing factors, a resulting goal is a desire to fabricate CMOS devices upon a single semiconductor substrate while accessing intrinsic mobility advantages of CMOS devices fabricated upon different semiconductor substrate channel crystallographic orientations.